Integrated circuit (IC) devices may rely upon an elaborate system of conductive interconnects for wiring together transistors, resistors, and other IC components, which are formed on a semiconductor substrate. The technology for forming these interconnects is highly sophisticated and well understood by practitioners skilled in the art. In a typical IC device manufacturing process, many layers of interconnects are formed over a semiconductor substrate, each layer being electrically insulated from adjacent layers by an interposing dielectric layer. The surface of these interposing dielectric layers should be as flat, or planar as possible to avoid problems associated with optical imaging and step coverage, which could frustrate the proper formation and performance of the interconnects.
As a result, many planarization technologies have evolved to support the IC device manufacturing industry. One such technology is called chemical mechanical polishing or planarization (CMP). CMP may include the use of lapping machines and other chemical mechanical planarization processes to smooth the surface of a layer, such as a dielectric layer, to form a planar surface. This may be achieved by rubbing the surface with an abrasive material, such as a polish pad, to physically etch away rough features of the surface. Rubbing of the surface may be performed in the presence of certain chemicals that may be capable of chemically etching the surface as well. After a dielectric layer has been sufficiently smoothed using CMP, interconnects may be accurately and reliably formed on the resulting planar surface.
Metal CMP, such as copper (Cu) CMP, is one step in the damascene technology for sub-micron processes. Significant copper dishing and recessing (such as within an interlayer dielectric) may occur as a result of a combined effect of chemical and mechanical actions that lead to a larger copper etch rate as compared with a barrier layer etch rate (and oxide etch rate) on patterned wafers. Thus, metal features (such as interconnect lines) may be polished faster than other surfaces, leading to recessed and dished structures. At the same time, protruded oxide and interlayer dielectric (ILD) patterns may suffer from excessive stress and a larger polish rate, which may lead to erosion. Combined copper dishing, recess and oxide erosion may lead to overall resistance variation within the die and within the wafer, and possibly yield degradation either by dishing/erosion related metal CMP defects or by build-up of uneven topography over metal layers. Therefore, dishing and erosion is an issue in CMP processes.